DIRECT TO PHASE II: Modular Software Reference Implementation for Waveforms
U.S. Department of Defense – Navy (SBIR)
See all 29 calls from U.S. Department of Defense – Navy →- Funder
- U.S. Department of Defense – Navy (SBIR)
- Award amount
- Not specified
- Deadline
- January 6, 2027
- Eligible countries
- United States
Summary
SBIR topic DON27BZ02-DV029 (U.S. Department of Defense – Navy), Phase I and II. Open to U.S. small businesses. Opens: December 2, 2026. Closes: January 6, 2027. The Multifunctional Information Distribution System (MIDS) Program Office (PMA/PMW-101) is driving a critical architectural pivot in tactical data link (TDL) communications. Historically, the defense sector has relied heavily on FPGAs to host complex tactical waveforms due to strict RF timing constraints. However, as noted in recent software-defined radio (SDR) surveys, this hardware-centric approach suffers from severe developmental friction [Ref 1]. Programming FPGAs via Hardware Description Languages (HDL) requires lengthy synthesis, complex place-and-route cycles, and difficult timing closures. Because software compilation bypasses these physical routing and synthesis barriers, transitioning from HDL to high-order software languages (C/C++) on general-purpose architectures typically reduces development timelines by 50% to 80%—compressing multi-year hardware upgrade cycles into a matter of months. To overcome legacy constraints, this initiative mandates a transition toward a modular open systems architecture (MOSA). By decoupling the physical layer (PHY) from the underlying hardware, containerized Software-Defined Waveforms (SDWs) can be deployed across modern processing. Because standard Central Processing Units (CPUs) often lack the deterministic throughput required for heavy RF pipelines, modern SDR frameworks dynamically offload computationally intensive PHY tasks to coprocessors like GPUs, Neural Processing Units (NPUs), or adaptive System-on-Chips (SoCs). This heterogeneous approach enables the execution of highly parallel mathematical pipelines via software Application Programming Interfaces (APIs), including: Vectorized Signal Processing on GPUs or NPU cores: • Executing Fast Fourier Transforms (FFTs) • High-throughput Forward Error Correction (FEC) • Matrix Multiplications AI-Driven…
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